------------------------------------------------//库声明
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

------------------------------------------------//实体定义
entity div_odd is
generic(data_width : integer := 20);
port
(    fpshu  : in std_logic_vector(data_width - 1 downto 0);
     clk_in : in std_logic;
    clk_out : out std_logic
	     );
end entity div_odd;

------------------------------------------------//结构体定义 
architecture behave of div_odd is

------------------------------------------------//信号量定义
signal count_1,count_2       : std_logic_vector(data_width - 1 downto 0);
signal clk_temp_1,clk_temp_2 : std_logic;

begin

------------------------------------------------//进程1，上升沿，计数比较
    process(clk_in)
    begin
        if clk_in'event and clk_in='1' then
            if count_1 < (conv_integer(fpshu)-1) then
                count_1 <= count_1 + 1;
            else count_1 <= (others => '0');
            end if;
            if count_1 < (conv_integer(fpshu)-1)/2 then
                clk_temp_1 <= '1';
            else clk_temp_1 <= '0';
            end if;
        end if;
    end process;

------------------------------------------------//进程2，下降沿，计数比较
    process(clk_in)
    begin
        if clk_in'event and clk_in='0' then
            if count_2 < (conv_integer(fpshu)-1) then
            count_2 <= count_2 + 1;
            else count_2 <= (others => '0');
            end if;
            if count_2 < (conv_integer(fpshu)-1)/2 then
                clk_temp_2 <= '0';
            else clk_temp_2 <= '1';
            end if;
        end if;
    end process;

------------------------------------------------//赋值	
    clk_out <= clk_temp_1 or clk_temp_2;

end architecture behave;